The present disclosure relates in general to semiconductor devices and their manufacture. More specifically, the present disclosure relates to the fabrication of a test structure macro to monitor dimensions (e.g., a depth) of deep trench isolation regions and local/shallow trench isolation regions.
Typical semiconductor devices are formed using active regions of a wafer. The active regions are defined by isolation regions used to separate and electrically isolate adjacent semiconductor devices. For example, in an integrated circuit having a plurality of metal oxide semiconductor field effect transistors (MOSFETs), each MOSFET has a source and a drain that are formed in an active region of a semiconductor layer by implanting n-type or p-type impurities in the layer of semiconductor material. Disposed between the source and the drain is a channel (or body) region. Disposed above the body region is a gate electrode. The gate electrode and the body are spaced apart by a gate dielectric layer.
One particularly advantageous type of MOSFET is known generally as a fin-type field effect transistor (FinFET). FIG. 1 depicts a three-dimensional view of an exemplary FinFET 100, which includes a “local” shallow trench isolation (STI) region 104 and a “deep” STI region 120 for isolation of active areas from one another. The basic electrical layout and mode of operation of FinFET 100 do not differ significantly from a traditional field effect transistor. FinFET 100 includes a semiconductor substrate 102, local STI region 104, deep STI region 120, a fin 106 and a gate 114, configured and arranged as shown. Fin 106 includes a source region 108, a drain region 110 and a channel region 112, wherein gate 114 extends over the top and sides of channel region 112. For ease of illustration, a single fin is shown in FIG. 1. In practice, FinFET devices are fabricated having multiple fins formed on local STI region 104 and substrate 102. Substrate 102 may be silicon, and local STI region 104 and deep STI region 120 may be an oxide (e.g., SiO2). Fin 106 may be silicon that has been enriched to a desired concentration level of germanium. Gate 114 controls the source to drain current flow (labeled ELECTRICITY FLOW in FIG. 1). In contrast to a planar MOSFET, however, source 108, drain 110 and channel 112 are built as a three-dimensional bar on top of local STI region 104 and semiconductor substrate 102. The three-dimensional bar is the aforementioned “fin 106,” which serves as the body of the device. The gate electrode is then wrapped over the top and sides of the fin, and the portion of the fin that is under the gate electrode functions as the channel. The source and drain regions are the portions of the fin on either side of the channel that are not under the gate electrode. The source and drain regions may be suitably doped to produce the desired FET polarity, as is known in the art. The dimensions of the fin establish the effective channel length for the transistor.
It is a challenge in FinFET manufacturing processes to form fins with uniform heights and widths. An “effective” dimension of a FinFET is usually different from the dimension that is selected during the device layout stage. This is because different fabrication processes inevitably results in some dimension offset during the manufacturing process. For example, current 10 nanometer FinFET devices employ both local STI regions and deep STI regions to isolate fins. Fabrication of local STI regions and deep STI regions in a FinFET include two-step oxide fills, oxide CMP (chemical mechanical polishing/planarization), oxide and nitride depositions as protection layers in the FIN regions during deep STI etching and CMP, HPO4 acid wet etch for nitride removal, and the like. The fin adjacent the deep STI region is known generally as the “last fin” and is highly susceptible to channel loss from local and deep STI region fabrication techniques. Material loss in the fin channel region degrades fin/device performance (e.g., high leakage currents, lower drive current, etc.) and can render multi-fin devices unsuitable for applications such as SRAM.